products and specifications discussed herein ar e subject to change by aptina without notice. MT9M112: 1/4-inch 1.3mp soc digital image sensor features 09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev. e 5/10 en 1 ?2005 aptina imaging corporation all rights reserved. 1/4-inch 1.3-megapixel soc cmos digital image sensor MT9M112 features ?aptina ? digitalclarity? cmos imaging technology ? system-on-a-chip (soc)?completely integrated camera system ? ultra-low power, low cost, progressive scan cmos image sensor ? on-die phase lock loop (pll) ? superior low-light performance ? on-die image flow processor (ifp) performs sophisticated processing: color recovery and correction, sharpening, gamma correction, lens shading correction, and on-the-fly defect correction ?programmable i/o slew rate ? 2 x 2 pixel binning ? mechanical shutter support ? filtered image downscaling to arbitrary size with smooth, continuous zoom and pan ? fully automatic xenon- and led-type flash support ? automatic features: auto exposure, auto white balance (awb), auto black reference (abr), auto flicker avoidance, auto color saturation, and auto defect identification and correction ? multiple parameter contexts, easy/fast mode switching ? camera control sequencer automates snapshots, snapshots with flash, and video clips ?simple two-wire serial programming interface ? itu-r bt.656 (ycbcr), 565rgb, 555rgb, or 444rgb formats (progressive scan) ? raw and processed bayer formats ?v dd power disable switch for reduced standby current ? four general purpose input bond pads applications ? cellular phones ?pdas ?toys ? other battery-powered products ordering information table 1: key performance parameters parameter value optical format 1/4-inch (5:4) active imager size 3.58mm(h) x 2.87mm(v) 4.59mm diagonal active pixels 1280h x 1024v pixel size 2.8 m x 2.8 m color filter array rgb bayer pattern shutter type electronic rolling shutter (ers) maximum data rate/ master clock 27 mps/54 mhz frame rate 15 fps at full resolution, 30 fps in preview mode (640 x 512) adc resolution 10-bit, on-chip responsivity 1.0v/lux-sec (550nm) dynamic range 68db snr max 44db supply voltage i/o digital 1.7vC3.1v core digital 1.7vC1.9v (1.8v nominal) analog 2.5vC3.1v (2.8v nominal) power consumption 170mw at 15 fps, full resolution 100mw at 30fps, preview mode operating junction temperature -30c to +70c packaging die table 2: available part numbers part number description MT9M112d00stc die
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev. e 5/10 en 2 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor table of contents table of contents applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 list of tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 internal architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 register notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 typical connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 signal descriptions: inputs, outputs and supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 general purpose inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 black level conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 digital gain and test pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 lens shading correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 interpolation, filtered resize, and aperture correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 defect correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 color correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 color saturation control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 itu-r bt.656 and rgb output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 details of bayer output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 additional output timing formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 automatic white balance (awb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 auto exposure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 automatic flicker detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 flash light control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 contexts and context switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 camera control sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 output data ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 reset, clocks, and low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 power supply skew during power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 v dd disable feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 pll operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 dc electrical specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 i/o parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 ac electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 timing parameters (1.8v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 timing parameters (2.8v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 output signal slew rate control (1.8v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 output signal slew rate control (2.8v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 two-wire serial interface specif ication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 spectral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev. e 5/10 en 3 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor list of tables list of tables table 1: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 3: signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 4: data ordering in ycbcr mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 5: output data ordering in processed bayer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 6: output data ordering in rgb mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 7: output data ordering in (8 + 2) bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 8: bayer output order r0x108[1:0] = 00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 9: bayer output order r0x108[1:0] = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 10: bayer output order r0x108[1:0] = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 11: bayer output order r0x108[1:0] = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 12: dc electrical characteristics and operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 13: i/o min/max parameters (vddq = 1.8v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 14: i/o min/max parameters (vddq = 2.8v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 15: i/o timing parameters (v dd q = 1.8v) 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 16: i/o timing parameters (v dd q = 2.8v) 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 17: output signal slew rate (1.8v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 18: output signal slew rate (2.8v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 19: two-wire serial interf ace timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 20: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev. e 5/10 en 4 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor list of figures list of figures figure 1: functional block diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 2: internal registers grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 3: typical configuration (connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 4: ifp block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 5: gamma correction curve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 6: power-up, reset, clock, and standby sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 7: power supply skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 8: vdd_dis shutdown sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 9: clock rise and fall ti ming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 10: i/o timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 11: two-wire serial interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 12: two-wire serial interface start and stop condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 13: typical spectral char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev.e 5/10 en 5 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor general description general description the aptina MT9M112 is an sxga-format, sing le-chip camera cmos active-pixel digital image sensor. this device combines the 2.8m image sensor core with fourth-genera- tion digital image flow processor technology from aptina. it captures high-quality color images at sxga resolution. the sxga cmos image sensor features digi talclarity?aptina?s br eakthrough low-noise cmos imaging technology that achieves cc d image quality (based on signal-to-noise ratio and low-light sensitivity), while maintaining the inherent size, cost, and integration advantages of cmos. the sensor is a complete solution designed specifically to meet the low-power, low-cost demands of battery-powered products such as cellular phones, pdas, and toys. it incor- porates sophisticated camera functions on-c hip and is programmab le through a simple two-wire serial interface. the MT9M112 performs sophisticated processing functions including color recovery, color correction, sharpening, programmable gamma correction, auto black reference clamping, auto exposure, automatic 50hz/60h z flicker avoidance, lens shading correc- tion, auto white balance (awb), and on-the-f ly defect identification and correction. additional features include day/night mode configurations, special camera effects such as sepia tone and solarization, and interpolat ion to arbitrary image size with continuous filtered zoom and pan. the device supports both xenon and led-type flash light sources in several snapshot modes. the device also has an on-board pll, and supports pixel binning as an enhanced form of image size reduction. the MT9M112 can be programmed to output progressive-scan images up to 30 fps. the image data can be output in any one of six 8-bit formats: ? itu-r bt.656 (formerly ccir656, progressive scan only) ycbcr ? 565rgb ? 555rgb ? 444rgb ? raw bayer ?processed bayer the frame_valid and line_valid signals are output on dedicated signals, along with a pixel clock that is sync hronous with valid data. functional overview the MT9M112 is a fully-automatic, single-c hip camera that requires only a power supply, lens, and clock source for basic oper ation. output video is streamed through a parallel 8-bit d out port as shown in figure 1 on page 8. the output pixel clock is used to latch data, while frame_valid and line_valid signals indicate the active video. the MT9M112 internal registers are configur ed using a two-wire serial interface. the device can be put in a low-power slee p mode by asserting standby and shutting down the clock. output signals can be tri-stated. both tri-stating output signals and entry in standby mode also can be achiev ed through the two-wire serial interface register writes. the MT9M112 accepts input clocks up to 54 mhz, delivering up to 30 fps for vga resolu- tion images.
MT9M112: 1/4-inch 1.3mp soc digital image sensor functional overview 09005aef81e5840a/09005aef81e57f44 aptina eserves the right to change products or specifications without notice. - rev.e 5/10 en 6 ?2005 aptina imaging corporation all rights reserved. internal architecture internally, the MT9M112 consists of a sensor core and an image flow processor (ifp). the ifp is divided in two sections: the colorpipe (cp) and the camera controller (cc). the sensor core captures raw bayer-encoded images that are then input in the ifp. the cp section of the ifp processes the incoming stream to create interpolated, color- corrected output, and the cc section controls the sensor core to maintain the desired exposure and color balance and to support snapshot modes. the sensor core, cp, and cc registers are grouped in three separate address spaces as shown in figure 2 on page 8. when accessing internal registers through the two-wire serial interface, select the desired address space by programming the r0xf0 (r240) register. the MT9M112 accelerates mode-switching wi th hardware-assisted context switching and supports taking snapshots, flash snapsh ots, and video clips using a configurable sequencer. the MT9M112 supports a range of color formats derived from four primary color repre- sentations: ycbcr, rgb, raw bayer (unpro cessed, directly from the sensor), and processed bayer (bayer format data regenerated from processed rgb). the device also supports a variety of output signaling/timing options: ? standard frame_valid/line_valid vide o interface with gated pixel clocks ? itu-r bt.656 marker-embedded video interf ace with either gated or uniform pixel clocks
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev.e 5/10 en 7 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor functional overview register notation the following register address notations are used in this document: ? r: example: r9:0?shutter width register (register 9) in the sensor page (page 0). used to uniquely specify a register. ? r0x<3 digit hex address> example: 0x106 ?mode control in page 1 register 0x6; leading digit signifies page number. ? data format (binary) column key in the register summary tables. the following key is used to indicate data format: ? = read only d = read/write 0 = reserved; read 0; must write 0 1 = reserved; read 1; must write 1 r = reserved; must write back value read ? the following key is used to indicate default value x = indeterminate register default values register definition table the register definition tables contain the po wer-on default values for the bit fields and registers of the MT9M112. modifying these va lues may [affect or degrade] the perfor- mance of the MT9M112. see the individual register descriptions for more detail. reserved registers do not alter the reserved registers. if some bits or bit patterns (that is, bit field values) in a register are reserved, they cannot be used. do not set bit fields to reserved or undefined bit patterns as aptina will not guarantee operation. the sensor registers are summarized in table 12 on page 1. the colorpipe registers are summarized in table 13 on page 5. the came ra control registers are summarized in table 14 on page 8. detailed register descriptions are given in table 15 on page 1, table 16 on page 1, and tabl e 17 on pag e 1.
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev.e 5/10 en 8 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor functional overview figure 1: functional block diagram note: each of the general purpose input only signals (gpi0Cgpi3) must be connected to either d gnd or v dd q for low-power consumption and reliable operation figure 2: internal registers grouping note: internal registers are grouped in three address spaces. register r0xf0 (r240) in each page selects the desired address space. sram line buffers image flow processor colorpipe image flow processor camera control image data control bus (two-wire serial interface transactions) pixel data sclk s data clkin standby v dd q/d gnd v dd /d gnd v aa /a gnd vaapix lens shading correction color interpolation filtered resize and zoom defect correction color correction gamma correction color conversion + formatting auto exposure auto white balance flicker detect/avoid camera control: snapshots, flash, video clip d out (7:0) pixclk frame_ valid line_ v ali d shutter control bus (two-wire serial interface transactions) + sensor control (gains, shutter, etc.) sensor core . 1280h x 1024v . 1/4-inch optical format . auto black compensation . programmable analog gain . programmable exposure . 10-bit adc . h/w context switch to/from preview . bayer rgb output control bus (two-wire serial interface transactions) MT9M112 flash v dd pll/pllgnd gpi0-gpi3 reset# vdd_dis image flow processor sensor core registers r[255:0] page 0 color pipeline registers r[255:0] page 1 camera control registers r[255:0] page 2
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev.e 5/10 en 9 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor typical connections typical connections figure 3 shows typical MT9M112 device connections. for low-noise operation, the MT9M112 requires separate power supplies for analog and digital. incoming digital and analog ground conductors can be tied togeth er next to the die. both power supply rails must be decoupled to ground using capacitors as close as possible to the die. the use of inductance filters is not recommended on the power supplies or output signals. the MT9M112 also supports different digital core (v dd /d gnd ) and i/o power (v dd q/ d gnd ) power domains that can be at different voltages. pll requires a clean power source (v dd pll). figure 3: typical configuration (connection) notes: 1. 1. a 1.5k resistor value is recommended for the two-wire serial interface r pull-up ; however, greater values may be used for slower transmission speeds. 2. MT9M112 standby can be connected to the customers asic controller directly, or to digital gnd, depending on the capability of the controller. 3. the pll bypass capacitor should be connected to v dd pll and d gnd . 4. do not leave general purpose input only signals, gpi0-gpi3, floating. must terminate to d gnd or v dd q. MT9M112 v dd qv dd v aa vaapix s addr standby clkin s data sclk test_enable reset # vdd_dis d gnd a gnd v dd pll core v dd disable standby mode two-wire serial interface clock input active low r eset rpull-up x 2 d out( 7:0)] pixclk line _valid frame _valid shutter flash to camera port analog ground digital ground gpi0-gpi3 to xenon or led flash driver general purpose input to mechanical shutter driver v dd qv dd v aa v dd pll vaapix digital i/o power pll power digital core power analog power
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev.e 5/10 en 10 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor signal descriptions: inputs, outputs and supply signal descriptions: inputs, outputs and supply all inputs and outputs are implemented with bidirectional buffers. care must be taken that all inputs are driven to avoid floating nodes. refer to the MT9M112 die data sheet (1/4-i nch 1.3-megapixel soc digital image sensor die features) document for pad number information. general purpose inputs logic levels of four general purpose inputs gpi0-gpi3 may be read through the two-wire serial interface facilitating pa ckaging identification. these signals must be terminated to either v dd q or d gnd to ensure that they are not floating. table 3: signal description name type supply reference description clkin input v dd q/d gnd master clock in sensor. reset# input v dd q/d gnd active low: asynchronous reset. s addr input v dd q/d gnd two-wire serial interface device id selection 1:0xba, 0:0x90. test_enable input v dd q/d gnd tie to d gnd for normal operation (manufacturing use only). sclk input v dd q/d gnd two-wire serial interface clock. standby input v dd q/d gnd multifunctional signal to control device addressing, power-down, and state functions (covering output enable function). vdd_dis input v dd q/d gnd disable core digital v dd for low power operation. gpi0-gpi3 input v dd q/d gnd general purpose inputs, do not leave floating; must terminate to either v dd q or d gnd . s data bidirectional v dd q/d gnd two-wire serial interface data i/o. d out 7-d out 0output v dd q/d gnd in normal mode, pixel data output: d out 7 is the most significant bit (msb), d out 0 is the least significant bit (lsb). in 10-bit, soc bypass mode, d out 0 is bit 2, d out lsb1 is bit 1, and d out lsb0 is bit 0. d out lsb1, d out lsb0 output v dd q/d gnd data out bit 1 and 0 in 10-bit soc bypass mode. frame_valid output v dd q/d gnd active high: frame_valid; indicates active frame. line_valid output v dd q/d gnd active high: line_valid; indicates active pixel. pixclk output v dd q/d gnd pixel clock output. flash output v dd q/d gnd active high: control external led or xenon flash devices. shutter output v dd q/d gnd active high: controls external mechanical shutter. a gnd supply v aa , vaapix analog ground. d gnd supply v dd , v dd q common digital core ground and digital i/o ground. v aa supply a gnd analog power. vaapix supply a gnd pixel array analog power supply. v dd supply d gnd core digital power. v dd q supply d gnd i/o digital power. v dd pll supply d gnd pll power. dnu C C factory test signal. do not connect.
MT9M112: 1/4-inch 1.3mp soc digital image sensor 09005aef81e5840a/09005aef81e57f44 aptina eserves the right to change products or specifications without notice. - rev. e 5/10 en 11 ?2005 aptina imaging corporation all rights reserved. the resulting interpolated rgb data passes through the current color correction matrix (ccm), saturation, and gamma corrections an d is formatted for final output.reducer and zoom window changes are synchronized so the reducer and zoom programming do not have to be coordinated with video frame timing. figure 4: the MT9M112 has 2d defect correction where pixels with values different from their neighbors by a programmable threshold are considered defects and are replaced.to obtain good color rendition and saturation, it is necessary to compensate for the differences between the spectral characteristics of th e imager color filter array and the spectral response of the human eye. this compensation is achieved through linear transformation of the image with a 3 x 3 element color correction matrix. optimum values for the color correction coefficients depend on the spectrum of the incident illumination and can either be programmed by the user, or automatically selected by the awb algorithm described in gamma correction curve the MT9M112 supports gradual color saturation reduction in the brightest areas of the image, helping eliminate color artifacts rela ted to clipped pixel values. for noise reduc- tion, both color saturation and sharpness enhancement can be set by the user or adjusted automatically by tracking the magnit ude of the gains used by the auto exposure algorithm. color saturation may be scaled by a constant value of either 0 percent (black and white), 25 percent (1/4), 37.5 percent (3/8), 50 percent (1/2), 75 percent (3/4), 100 percent (1/1), 112.5 percent (9/8), 125 percent (5/4), 137.5 percent (11/8), and 150 percent (3/2). gamma correction table, and output format gamma correction 0 64 128 192 256 0 256 512 768 1024 input rgb, 10-bit output rgb, 8-bit 0.5
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev. e 5/10 en 12 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor output data ordering the following tables describe the output da ta order depending on the mode selected. table 4: data ordering in ycbcr mode mode byte byte+1 byte+2 byte+3 default cb i y i cr i y i+1 swap red and blue cr i y i cb i y i+1 swap bytes y i cb i y i+1 cr i swap red and blue, swap bytes y i cr i y i+1 cb i table 5: output data ordering in processed bayer mode mode line byte byte+1 byte+2 byte+3 default first g i r i+1 g i+2 r i+3 second b i g i+1 b i+2 g i+3 flip bayer column first r i g i+1 r i+2 g i+3 second g i b i+1 g i+2 b i+3 flip bayer row first b i g i+1 b i+2 g i+3 second g i r i+1 g i+2 r i+3 flip bayer column flip bayer row first g i b i+1 g i+2 b i+3 second r i g i+1 r i+2 g i+3 table 6: output data ordering in rgb mode mode (swap disabled) byte d7 d6 d5 d4 d3 d2 d1 d0 rgb565 first r7 r6 r5 r4 r3 g7 g6 g5 second g4 g3 g2 b7 b6 b5 b4 b3 rgb555 first 0 r7 r6 r5 r4 r3 g7 g6 second g5 g4 g3 b7 b6 b5 b4 b3 rgb444x first r7 r6 r5 r4 g7 g6 g5 g4 secondb7b6b5b40000 rgbx444 first 0 0 0 0 r7 r6 r5 r4 second g7 g6 g5 g4 b7 b6 b5 b4 table 7: output data ordering in (8 + 2) bypass mode mode byte d7 d6 d5 d4 d3 d2 d1 d0 8 + 2 bypassfirstb9b8b7b6b5b4b3b2 second000000b1b0
MT9M112: 1/4-inch 1.3mp soc digital image sensor 09005aef81e5840a/09005aef81e57f44 aptina eserves the right to change products or specifications without notice. - rev. e 5/10 en 13 ?2005 aptina imaging corporation all rights reserved. table 8: bayer output order r0x108[1:0] = 00 r0x108[1] vertical r0x108[0] horizontal column row 1st 2nd 3rd 4th 00firstgrgr secondbgbg table 9: bayer output order r0x108[1:0] = 01 r0x108[1] vertical r0x108[0] horizontal column row 1st 2nd 3rd 4th 01firstrgrg secondgbgb table 10: bayer output order r0x108[1:0] = 10 r0x108[1] vertical r0x108[0] horizontal column row 1st 2nd 3rd 4th 10firstbgbg second g r g r table 11: bayer output order r0x108[1:0] = 11 r0x108[1] vertical r0x108[0] horizontal column row 1st 2nd 3rd 4th 11firstgbgb second r g r g
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev. e 5/10 en 14 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor
MT9M112: 1/4-inch 1.3mp soc digital image sensor 09005aef81e5840a/09005aef81e57f44 aptina eserves the right to change products or specifications without notice. - rev. e 5/10 en 15 ?2005 aptina imaging corporation all rights reserved.
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev. e 5/10 en 16 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor
MT9M112: 1/4-inch 1.3mp soc digital image sensor 09005aef81e5840a/09005aef81e57f44 aptina eserves the right to change products or specifications without notice. - rev. e 5/10 en 17 ?2005 aptina imaging corporation all rights reserved.
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev. e 5/10 en 18 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor
MT9M112: 1/4-inch 1.3mp soc digital image sensor 09005aef81e5840a/09005aef81e57f44 aptina eserves the right to change products or specifications without notice. - rev. e 5/10 en 19 ?2005 aptina imaging corporation all rights reserved.
MT9M112: 1/4-inch 1.3mp soc digital image sensor reset, clocks, and low power modes 09005aef81e5840a/09005aef81e57f44 aptina eserves the right to change products or specifications without notice. - rev. e 5/10 en 21 ?2005 aptina imaging corporation all rights reserved. reset, clocks, and low power modes there are no constraints concerning the or der in which the various power supplies are applied; however, the MT9M112 requires reset in order to operate properly at power-up. refer to the figure 6 for the power-up, reset, and standby sequences. figure 6: power-up, reset, clock, and standby sequence notes: 1. all output signals are defined during initial power-up with reset# = 0 without clkin being active. for a proper reset sequence for the rest of the sensor, during initial powerup, assert reset# = 0 for at least 1 s after all power supplies have stabilized and clkin is active (being clocked). driving reset# = 0 does not put the part in a low power state. 2. in hard standby the output signals are high impedance by default. the output state is controlled by reg- ister r0x00d settings. 3. soft standby is asserted or deasserted by a two-wire serial interface to r0x00d[2]. in this mode, the ana- log clock and the internal clocks are shut off. the output signals are not high impedance by default. the total leakage currents can be lowered if the two-wire serial interface and the clkin are turned off after 80 clkin cycles after issuing soft standby. 4. wait for 10 clkin rising edges after reset# is deasserted before using two-wire serial interface. 5. illustration not drawn to scale (do not count number of clock pulses). clkin two-wire serial i/f sclk , s data reset # v dd , v dd q , v dd pll , v aa , vaapix data output standby (hard standby) vdd _dis min 10 clkin cycles high-z pre-standby standby wake up active d out (7:0) r0x00d[4] = 0, r0x00d[6] = 0 driven = 0 low-power non-low-power does not respond to serial interface when standby = 1 d out [7:0] power up non-low-power 200ms min 80 clkin cycles min 10 clkin cycles active power down d out [7:0]
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev. e 5/10 en 22 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor reset, clocks, and low power modes power supply skew during power up there are no constraints concerning the order in which the various power supplies areapplied to the part. as long as a hardwa re reset is asserted following the stabiliza- tionof supplies, the part will be properly initialized. however, to minimize power consumption,all power supplies must be simult aneously applied with no more than 1ms of skew. see figure 7 for more details. figure 7: power supply skew 1ms v dd v dd pll v dd q v aa vaapix
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev. e 5/10 en 23 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor reset, clocks, and low power modes figure 8: vdd_dis shutdown sequence note: illustration not drawn to scale (do not count number of clock pulses). pre- shutdown shut down wake up active low power non-low-power power up non-low-power clkin two-wire serial i/f sclk , s data reset# v dd pll , v dd, v ddq v aa , vaapix data output standby (hard standby) vdd_dis min 10 clkin cycles high-z d out (7:0) r0x00d[4] = 0, r0x00d[6] = 0 driven = 0 min 80 clkin cycles does not respond to serial interface when standby = 1 min 5 clkin cycles d out [7:0] 200ms min 10 clkin cycles driven = 0 64 clkin cycles optional to assert reset# = 0 d out [7:0] power down active
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev. e 5/10 en 24 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor reset, clocks, and low power modes v dd disable feature the vdd_dis signal is used to shut down digital core v dd reducing the power consump- tion significantly during standby. all register settings are lost. however, the output signal states are maintained as long as v dd q is maintained. output signals must be configured appropriately during the standby sequence. input signal transitions (including reset#) during vdd_dis = 1 are ignored. proper shutdown and recovery sequences must be followed for minimum power consumption. disable and enable the core v dd using the vdd_dis signal with the following sequences. to enter low power state 1. pll bypass r0x065[15] = 1 2. pll into standby/power down 3. enter standby mode (hardware or software) 4. assert vdd_dis 5. stop clkin 6. deassert standby if asserted 7. the part is now in a core v dd shutdown low power state to exit low power state 1. assert reset# (optional) 2. assert standby if the output must be high impedance during start-up 3. deassert vdd_dis 4. start clkin 5. deassert reset# (if asserted in st ep 1 above) and start up the sensor
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev. e 5/10 en 25 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor reset, clocks, and low power modes pll operation the sequence to turn on pll is: 1. after the chip power on reset, pll is in bypass mode by default. 2. program pll parameters m, n, and p in r0x066 and r0x067 depending on the external clock frequency and target cloc k frequency. pll output clock frequency ( f out) is calculated with the following equation: (eq 1) where f clkin is external clock frequency, n is pre-divider and p is post-divider. both registers have a default value of ?1.? 3. wake up pll by programming r0x065[14] = 0. 4. wait at least 1ms for pll to stabilize. 5. program r0x065[15] = 0 to enable pll output to clock core and release pll bypass. f out f clkin m 1 2 n 1 + () p 1 + () -------------------- ----------------- -------------- ?? ?? =
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev. e 5/10 en 1 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor electrical specifications electrical specifications dc electrical specification table 12 defines the main power supply vo ltages and operating conditions of the MT9M112. table 12: dc electrical characteristics and operating conditions note: 1. power consumption numbers do not include power from v dd q. setup conditions: t j = -30c to +70c, unless otherwise specified. symbol definition condition min typ max unit v dd core digital voltage 1.7 1.8 1.9 v v dd q i/o digital voltage 1.7 1.8v or 2.8v 3.1 v v aa analog voltage 2.5 2.8 3.1 v vaapix pixel supply voltage 2.5 2.8 3.1 v v dd pll pll analog voltage 2.5 2.8 3.1 v leakage current standby = v dd q (asserted) vdd_dis = v dd q (asserted) clkin = 0v (no clocks running) CC10 a standby = v dd q (asserted) vdd_dis = 0v (deasserted) clkin = 0v (no clocks running) CC300 a operating power consumption 1 sxga @ 15 fps C 170 C mw vga @ 30 fps, binning enabled C 100 C t j operating junction temperature -30 C +70 c
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev. e 5/10 en 2 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor electrical specifications i/o parameters table 13 and table 14 define threshold parameters for voltage and current on input and output signals. table 13: i/o min/max parameters (v dd q = 1.8v) setup conditions: v dd =1.8v, v dd q = 1.8v, v aa = 2.8v, vaapix = 2.8v, v dd pll = 2.8v, t j = -30c to +70c, unless otherwise specified . table 14: i/o min/max parameters (v dd q = 2.8v) setup conditions: v dd =2.8v, v dd q = 2.8v, v aa = 2.8v, vaapix = 2.8v, v dd pll = 2.8v, t j = -30c to +70c, unless specified otherwise symbol definition condition miin max unit v ih input high voltage i ih = -10 ?a 1.7 C v v il input low voltage i il = 10 ?a C 0.3 v v oh output high voltage i oh = -9ma v dd q - 0.4 C v ol output low voltage i ol = 9ma C 0.4 i oh output high current v oh = 1.5v C -6 ma i ol output low current v ol = 0.3v C 6 ma i l input leakage current v in = 0v or v dd q all signals including output pins in high impedance state C5 a v in = 3.1v; v dd = 0v, v dd q = 0v, v aa = 0v, vaapix = 0v, v dd pll = 0v s data and sclk signals only C5 a symbol definition condition miin max unit v ih input high voltage i ih = -10 a2.5Cv v il input low voltage i il = 10 aC0.3v v oh output high voltage i oh = -15ma v dd q - 0.4 C v v ol output low voltage i ol = 15ma C 0.4 v i oh output high current v oh = 2.5v C -11 ma i ol output low current v ol = 0.3v C 11 ma i l input leakage current v in = 0v or v dd q all signals including output pins in high impedance state C5 a v in = 3.1v; v dd = 0v, v dd q = 0v, v aa = 0v, vaapix = 0v, v dd pll = 0v s data and sclk signals only C5 a
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev. e 5/10 en 3 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor electrical specifications ac electrical specification figure 9 and figure 10 illustrate clock and i/o timing and show the timing relationships that are defined in table 15 on page 4. figure 9: clock rise and fall timing figure 10: i/o timing diagram notes: 1. see figure 8 for rise and fall timing details. 2. pll disabled for t cp. pixclk is in phase with clkin with propagation delay of t cp by default (solid line) and could be inverted (dashed line). 90% 10% 90% 10% f t r t 100% v dd q 0v sr icr = (90% - 10%) * v dd q t r sr icf = (90% - 10%) * v dd q t f clkin pixclk 2 t clkin data(7:0) frame_valid/ line_valid xxx xxx xxx xxx xxx xxx t cp t pfl t pll t dvp t pfh t plh pxl_0 pxl_1 pxl_2 pxl_n t pdv note 1
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev. e 5/10 en 4 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor electrical specifications timing parameters (1.8v) table 15 defines timing parameters for the main clocks and the timing relationship between clocks and valid data. table 15: i/o timing parameters (v dd q = 1.8v) 1 ac setup conditions: f clkin = 48 mhz, v dd =1.8v, v dd q = 1.8v, v aa = 2.8v, vaapix = 2.8v, v dd pll = 2.8v, output load = 15pf, t j = -30c to +70c , unless otherwise specified. notes: 1. output signals d out (7:0), line_valid (lv), and frame_valid (fv) are not synchronized with pixclk and thus may lag or lead pixclk. therefore, t pdv, t dvp, t pfh, t plh, and t pfl may be positive or negative. 2. two pixclk cycles are missing prior to falling edge of lv. t pll for pixclk = 48 mhz. 3. slew rates for input clock rising edge ( sr icr) and falling edge ( sr icf) should not differ by more than 10%. symbol definition condition min typ max unit f clkin1 input clock frequency pll enabled 6 48 54 mhz t clkin1 input clock period pll enabled 18.5 20.8 166.6 ns f clkin2 input clock frequency pll disabled 6 48 54 mhz t clkin2 input clock period pll disabled 18.5 20.8 166.6 ns sr icr 3 input clock rising edge slew rate clkin = 54 mhz 0.70 C C v/ns clkin = 27 mhz 0.40 C C v/ns clkin = 13.5 mhz 0.23 C C v/ns sr icf 3 input clock falling edge slew rate clkin = 54 mhz 0.70 C C v/ns clkin = 27mhz 0.40 C C v/ns clkin = 13.5mhz 0.23 C C v/ns d clkin input clock duty cycle clkin = 54 mhz 45 50 55 % t jitter input clock jitter clkin = 54 mhz C C 0.15 ns t cp clkin to pixclk propagation delay pll disabled C 12 C ns f pixclk pixclk frequency pll enabled or disabled 6 48 54 mhz d pixclk pixclk output duty cycle pll enabled or disabled 40 50 60 % t pdv pixclk to data valid -2 C 2 ns t dvp data valid to pixclk -2 C 2 ns t pfh pixclk to fv high -2 C 2 ns t plh pixclk to lv high -2 C 2 ns t pfl pixclk to fv low -2 C 2 ns t pll 2 pixclk falling edge to lv falling edge 39.7 C 43.7 ns f vco vco frequency 110 C 240 mhz f pfd phase frequency detector 2 C 13.75 mhz c in input signal capacitance C 3.5 C pf c load load capacitance C C 30 pf
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev. e 5/10 en 5 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor electrical specifications timing parameters (2.8v) table 16: i/o timing parameters (v dd q = 2.8v) 1 ac setup conditions: f clkin = 48 mhz, v dd =1.8v, v dd q = 2.8v, v aa = 2.8v, vaapix = 2.8v, v dd pll = 2.8v, output load = 15pf, t j = -30c to +70c, unless otherwise specified. notes: 1. output signals d out (7:0), line_valid (lv), and frame_valid (fv) are not synchronized with pixclk and thus may lag or lead pixclk. therefore, t pdv, t dvp, t pfh, t plh, and t pfl may be positive or negative. 2. two pixclk cycles are missing prior to falling edge of lv. t pll for pixclk = 48 mhz. 3. slew rates for input clock rising edge ( sr icr) and falling edge ( sr icf) should not differ by more than 10%. symbol definition condition min typ max unit f clkin1 input clock frequency pll enabled 6 48 54 mhz t clkin1 input clock period pll enabled 18.5 20.8 166.6 ns f clkin2 input clock frequency pll disabled 6 48 54 mhz t clkin2 input clock period pll disabled 18.5 20.8 166.6 ns sr icr 3 input clock rising edge slew rate clkin = 54 mhz 1.10 C C v/ns clkin = 27 mhz 0.62 C C v/ns clkin = 13.5 mhz 0.36 C C v/ns sr icf 3 input clock falling edge slew rate clkin = 54 mhz 1.10 C C v/ns clkin = 27mhz 0.62 C C v/ns clkin = 13.5mhz 0.36 C C v/ns d clkin input clock duty cycle clkin = 54 mhz 45 50 55 % t jitter input clock jitter clkin = 54 mhz C C 0.15 ns t cp clkin to pixclk propagation delay pll disabled C12Cns f pixclk pixclk frequency pll enabled or disabled 6 48 54 mhz d pixclk pixclk output duty cycle pll enabled or disabled 40 50 60 % t pdv pixclk to data valid -2 C 2 ns t dvp data valid to pixclk -2 C 2 ns t pfh pixclk to fv high -2 C 2 ns t plh pixclk to lv high -2 C 2 ns t pfl pixclk to fv low -2 C 2 ns t pll 2 pixclk falling edge to lv falling edge 39.7 C 43.7 ns f vco vco frequency 110 C 240 mhz f pfd phase frequency detector 2 C 13.75 mhz c in input signal capacitance C 3.5 C pf c load load capacitance C C 30 pf
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev. e 5/10 en 6 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor electrical specifications output signal slew rate control (1.8v) table 17 and table 18 show the codes for adjusting the slew rate of output signals. table 17: output signal slew rate (1.8v) setup conditions: v dd q = 1.8v, output load c load = 15pf, t j = -30c to +70c , unless otherwise specified. output signal slew rate control (2.8v) table 18: output signal slew rate (2.8v) setup conditions: v dd q = 2.8v, output load c load = 15pf, t j = -30c to +70c , unless otherwise specified. signals parameter definition min typ max unit d out [7:0], fv, lv, flash, shutter, pixclk, s data sr hl , sr lh output slew rate, code 0, slowest 0.12 C 0.14 v/ns code 1 0.13 C 0.16 code 2 0.14 C 0.17 code 3 0.16 C 0.19 code 4 0.18 C 0.22 code 5 0.20 C 0.25 code 6 0.24 C 0.29 code 7, fastest 0.30 C 0.35 signals parameter definition min typ max unit d out [7:0], fv, lv, flash, shutter, pixclk, s data sr hl , sr lh output slew rate, code 0, slowest 0.32 C 0.35 v/ns code 1 0.37 C 0.41 code 2 0.42 C 0.46 code 3 0.48 C 0.52 code 4 0.58 C 0.63 code 5 0.73 C 0.78 code 6 0.97 C 1.05 code 7, fastest 1.65 C 1.73
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev. e 5/10 en 7 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor electrical specifications two-wire serial interface specification the following diagrams illustrates the two-wire serial interface bus timing. figure 11: two-wire serial interface timing diagram figure 12: two-wire serial interface start and stop condition timing table 19: two-wire serial interface timing f sclk = 400khz, v dd =1.8v, v aa = 2.8v, vaapix = 2.8v, v dd q = 2.8v, t j = -30c to +70c, unless otherwise specified. symbol definition min typical max units f sclk two-wire serial interface input clock frequency 400 khz t ic two-wire serial interface clock period 2500 ns t ich two-wire serial interface clock period high 1250 ns t icl two-wire serial interface clock period low 1250 ns t iss setup time for start condition 625 ns t ihs hold time for start condition 416.7 ns t isd setup time for input data 625 ns t ihd hold time for input data 625 ns t oaa output data acknowledge time 1250 ns t oda output data delay time 1250 ns t isp setup time for stop condition 625 ns t ihp hold time for stop condition 625 ns c insi serial interface input pin capacitance 3.5 pf c loadsd s data max load capacitance 30 pf r sd s data pull-up resistor 1.5 k s clk s data (input to sensor) s data (ouput from sensor) t ic t icl t ich t iss t ihd t isd t oaa t oda t isp sc lk t ihs t ihp s data (input to sensor)
MT9M112: 1/4-inch 1.3mp soc digital image sensor electrical specifications 09005aef81e5840a/09005aef81e57f44 aptina eserves the right to change products or specifications without notice. - rev. e 5/10 en 8 ?2005 aptina imaging corporation all rights reserved. absolute maximum ratings note: stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating con- ditions for extended periods may adversely affect reliability. table 20: absolute maximum ratings symbol definition condition min max unit v supply power supply voltage (all supplies) d gnd =0v, a gnd =0v -0.3 4.0 v i supply total power supply current C 150 ma i gnd total gnd current C 150 ma v in dc input voltage all signals except s data and sclk -0.3 v dd q + 0.3 v s data and sclk signals, v dd q = 0v -0.3 3.6 v v out dc output voltage -0.3 v dd q + 0.3 v t stg storage temperature -40 +85 c
09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev. e 5/10 en 9 ?2005 aptina imaging corporation. all rights reserved. MT9M112: 1/4-inch 1.3mp soc digital image sensor spectral characteristics spectral characteristics figure 13: typical spectral characteristics relative spectral response 0.0 0.2 0.4 0.6 0.8 1.0 1.2 350 450 550 650 750 85 0 950 1050 wavelength (nm) relative response blue green red
10 eunos road 8 13-40, singapore post center, singapore 408600 prodmktg@aptina.com www.aptina.com aptina, aptina imaging, digitalclarity, and the aptina logo are the property of aptina imaging corporation all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. alt hough considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. MT9M112: 1/4-inch 1.3mp soc digital image sensor revision history 09005aef81e5840a/09005aef81e57f44 aptina reserves the right to change products or specifications without notice. - rev. e 5/10 en 10 ?2005 aptina imaging corporation all rights reserved. revision history rev. e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/10 ? updated to non-confidential rev. d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/10 ? updated to aptina template rev. c, production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/06 ? added power supply skew, figure 7 on page 22. ? added register r0x2ca (context control program status and debug). ? upgraded data sheet to production. ? updated power consumption numbers in table 12 on page 1 from max to typ. ? update to flash description table 3 on page 10. ? changed resize/zoom to resize on various pages. ? added new data ( f vco and f pfd) to table 15 on page 4 and table 16 on page 5. ? updated figure 11 on page 7 and figure 12 on page 7. ?updated t oaa to max column. ? updated r0x2c8[13] to reserved. ? removed unused registers. rev. b, preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12/05 ? updated register summary, see "sensor core registers ? summary" on page 1 ? updated detailed register tables, see "page 0: sensor core register descriptions" on page 1, "page 1: image processing register descriptions" on page 1 and "page 2: camera control register descriptions" on page 1 ? updated electrical specifications, see "electrical specifications" on page 1 rev. a, advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/05 ?initial release
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